This thesis presents the development of a low-power analog-to-digital converter (ADC) which is intended to be used in WPAN receivers. WPAN devices are usually mobile and, therefore, operate on batteries. This puts a strict limitation on the power dissipation of WPAN systems. One common problem in WPAN systems is the overspecification problem. The receiver, which has to satisfy the requirements under demanding conditions, operates as overspecified when the conditions are not demanding. This reduces the power efficiency of WPAN systems. Other problems of WPANs include market segmentation and high design margins due to process variations. All these problems result in reduced power efficiency. In this project, adaptive reconfiguration concept is proposed. Adaptive reconfigurability concept is based on the idea that environment-aware systems can prevent the power inefficiencies by reconfiguring themselves to the desired level of performance. Moreover, in this thesis, best alternative selection method which is a statistical mismatch compensation method is proposed. This method aims to eliminate the high area and power cost of the conventional mismatch compensation techniques. In order to demonstrate the proposed techniques, a low-power, 25 MS/s SAR ADC which is reconfigurable between 5-12 bits is designed. It utilizes best alternative selection method for mismatch compensation in its DAC array and comparator. Simulation results show that the analog power dissipation of the ADC can be scaled efficiently which verifies the reconfiguration concept. The designed ADC is fabricated in TSMC 65 nm standard CMOS. It occupies a silicon area of 997.8 μm X 2040 μm. Operational tests show that the ADC functions properly. The comparator offset whose simulated RMS value is 14.6 mV and whose RMS value for 64 tested comparators is 19.83 mV is brought to only 0.29 mV as a result of calibration. This is a result which proves the power of best alternative selection methods. The DAC array could not yet be calibrated since its calibration will take more time than expected because of the noise floor which is 12.5 dB higher than its expected value during the design phase.