000186376 001__ 186376
000186376 005__ 20190316235630.0
000186376 037__ $$aCONF
000186376 245__ $$aOLTP in Wonderland -- Where do cache misses come from in major OLTP components?
000186376 269__ $$a2013
000186376 260__ $$bACM$$c2013
000186376 336__ $$aConference Papers
000186376 500__ $$aSYSTEMS PUBLICATION_SHORE_MT
000186376 520__ $$aFor several decades, online transaction processing has been one of the main applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Despite the novel approaches from industry and various research proposals from academia, recent studies emphasize that OLTP workloads still cannot exploit the full capability of modern processors. To better integrate OLTP and hardware in future systems, we perform a detailed analysis of instruction and data misses, the main causes of memory stalls. We demonstrate which operations and components of a typical storage manager cause the majority of different types of misses in each level of the memory hierarchy on a configuration that closely represents modern commodity hardware. We also observe the impact of data working set size on these misses. According to our experimental results, L1 instruction misses are an extensive cause of the overall stall time for OLTP even for data working set sizes as large as 100GB as long as the data fits in memory. Capacity misses coming from the index probe operation are the dominant cause of the instruction and data stalls when running typical OLTP workloads. During index probe (one of the most common operations in OLTP), the B-tree, lock, and buffer management components of a storage manager are responsible for more than half of the total misses.
000186376 6531_ $$aOLTP
000186376 6531_ $$aShore-MT
000186376 6531_ $$aCache Misses
000186376 6531_ $$aMicro-architectural Analysis
000186376 700__ $$0244143$$g190851$$aTözün, Pinar
000186376 700__ $$aGold, Brian
000186376 700__ $$aAilamaki, Anastasia$$g177957$$0243527
000186376 7112_ $$dJune 24, 2013$$cNew York, New York, USA$$a9th International Workshop on Data Management on New Hardware
000186376 773__ $$tProceedings of the 9th International Workshop on Data Management on New Hardware$$q8:1--8:6
000186376 8564_ $$uhttp://dl.acm.org/citation.cfm?id=2485286$$zURL
000186376 8564_ $$uhttps://infoscience.epfl.ch/record/186376/files/damon2013_tozun.pdf$$zn/a$$s284937$$yn/a
000186376 909C0 $$xU11836$$0252224$$pDIAS
000186376 909CO $$ooai:infoscience.tind.io:186376$$qGLOBAL_SET$$pconf$$pIC
000186376 917Z8 $$x190851
000186376 917Z8 $$x190851
000186376 917Z8 $$x190851
000186376 917Z8 $$x190851
000186376 937__ $$aEPFL-CONF-186376
000186376 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000186376 980__ $$aCONF