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A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices
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A High-Level Synthesis Flow for the Implementation[...]
-
Nacci, Alessandro Antonio
et al
main
file(s):
DAC2013-a52
version 1
DAC2013-a52.pdf
[710.69 KB]
03 Nov 2020, 13:55
Publisher's version