A Background Calibration Method for DAC Mismatch Correction in Multibit Sigma-Delta Modulators

A topology for the calibration of DAC errors in multi-bit sigma delta modulators is presented. The proposed technique enables the calibration to proceed in the background. In this technique, two DACs are used in a time-interleaved fashion. One DAC is calibrated at a time while the other is connected to the modulator. The technique is demonstrated by a design in UMC 0.18 µm CMOS technology which shows a very competitive figure of merit of 78fJ/Conv-Step. The extensive simulation results are presented to validate the results.


Presented at:
International SoC Design Conference (ISOCC), South Korea, Nov 4- 7
Year:
2012
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 Record created 2013-02-20, last modified 2018-03-17

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