Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems

Ultra-low-power (ULP) software-programmable architectures are gradually replacing 
dedicated VLSI circuits in many applications, including health care and other critical areas. However, the cost for more flexibility is the less frugal use of energy. This cost can be partially recovered by aggressive supply voltage scaling, often deep into the sub-threshold regime, which, however, raises concerns on performance, standby leakage, and reliability. In this talk, we will discuss some of the issues and possible solutions to ULP computing and embedded systems desigm at scaled voltages. We will discuss architectural choices and circuit level aspects and illustrate them with examples including robust Sub-VT memories, ULP multi-core systems, and Sub-VT application specific processors.


Presented at:
Winter School on Design Technologies for Heterogeneous Embedded Systems (FETCH), Leysin, Vaud, Switzerland, January 7-9, 2013
Year:
2013
Keywords:
Note:
Keynote
Laboratories:




 Record created 2013-02-01, last modified 2018-03-17

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