Loading...
conference paper
A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
2013
Proceedings of the 2013 International Solid-State Circuits Conference (ISSCC)
An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redundant capacitive DAC with constant common mode. Background comparator offset compensation is implemented. The ADC consumes 3.1mW from a 1V supply and occupies 0.0015mm2.
Type
conference paper
Authors
•
•
Schmatz, Martin
•
Francese, P. A.
•
Menolfi, C.
•
Braendli, M.
•
Kossel, M.
•
Morf, T.
•
Meyer Anderson, T.
•
Publication date
2013
Published in
Proceedings of the 2013 International Solid-State Circuits Conference (ISSCC)
Publisher place
San Francisco, California
Peer reviewed
REVIEWED
EPFL units
Event name | Event place | Event date |
San Francisco, California, USA | February 17-21, 2013 | |
Available on Infoscience
January 26, 2013
Use this identifier to reference this record