Conference paper

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redundant capacitive DAC with constant common mode. Background comparator offset compensation is implemented. The ADC consumes 3.1mW from a 1V supply and occupies 0.0015mm2.


    • EPFL-CONF-183333

    Record created on 2013-01-26, modified on 2017-05-10


  • There is no available fulltext. Please contact the lab or the authors.

Related material