A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
Kull, Lukas; Toifl, Thomas; Schmatz, Martin; Francese, P. A.; Menolfi, C.; Braendli, M.; Kossel, M.; Morf, T.; Meyer Anderson, T.; Leblebici, Yusuf
2013

Abstract

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redundant capacitive DAC with constant common mode. Background comparator offset compensation is implemented. The ADC consumes 3.1mW from a 1V supply and occupies 0.0015mm2.

Details

Title A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
Author(s) Kull, Lukas ; Toifl, Thomas ; Schmatz, Martin ; Francese, P. A. ; Menolfi, C. ; Braendli, M. ; Kossel, M. ; Morf, T. ; Meyer Anderson, T. ; Leblebici, Yusuf
Published in Proceedings of the 2013 International Solid-State Circuits Conference (ISSCC)
Conference 2013 International Solid-State Circuits Conference (ISSCC), San Francisco, California, USA, February 17-21, 2013
Date 2013
Publisher San Francisco, California
Laboratories LSM
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date 2013-01-26

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