A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redundant capacitive DAC with constant common mode. Background comparator offset compensation is implemented. The ADC consumes 3.1mW from a 1V supply and occupies 0.0015mm2.


Published in:
Proceedings of the 2013 International Solid-State Circuits Conference (ISSCC)
Presented at:
2013 International Solid-State Circuits Conference (ISSCC), San Francisco, California, USA, February 17-21, 2013
Year:
2013
Publisher:
San Francisco, California
Laboratories:




 Record created 2013-01-26, last modified 2018-09-13


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