Offset Compensation Based on Distributed Hall Cell Architecture

A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current level in each block can be adjusted according to the requirements in terms of offset, offset drift and signal to noise ratio. A chip was fabricated in 0.35 µm CMOS standard technology to demonstrate the potential of this architecture. The chip shows promising results, and in particular, a very low offset drift was observed at the front-end output stage (of the order of 10 nT/°C).


Published in:
IEEE Transactions on Magnetics Mag, 49, 1, 105-108
Year:
2013
Publisher:
Institute of Electrical and Electronics Engineers
ISSN:
0018-9464
Keywords:
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2013-01-23, last modified 2018-03-17

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