A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current level in each block can be adjusted according to the requirements in terms of offset, offset drift and signal to noise ratio. A chip was fabricated in 0.35 µm CMOS standard technology to demonstrate the potential of this architecture. The chip shows promising results, and in particular, a very low offset drift was observed at the front-end output stage (of the order of 10 nT/°C).