Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self - checking ripple - carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style.


Published in:
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 19-23, 2013
Year:
2013
Laboratories:




 Record created 2013-01-15, last modified 2018-03-17

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