000183096 001__ 183096
000183096 005__ 20190316235543.0
000183096 037__ $$aCONF
000183096 245__ $$aDual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs
000183096 269__ $$a2013
000183096 260__ $$c2013
000183096 336__ $$aConference Papers
000183096 520__ $$aWe extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions for dual-threshold-voltage design using a wiring scheme, to target either high-performance or low-leakage applications. Synthesis of benchmark circuits with these devices shows comparable performance and 54% reduction of leakage power consumption compared to FinFET technology
000183096 700__ $$0245831$$g212096$$aZhang, Jian
000183096 700__ $$aGaillardon, Pierre-Emmanuel
000183096 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000183096 7112_ $$dMay 19-23, 2013$$cBeijing, China$$aIEEE International Symposium on Circuits and Systems (ISCAS)
000183096 773__ $$tProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
000183096 8564_ $$uhttps://infoscience.epfl.ch/record/183096/files/JZ_ISCAS13.pdf$$zn/a$$s460473$$yn/a
000183096 909C0 $$xU11140$$0252283$$pLSI1
000183096 909CO $$pIC$$ooai:infoscience.tind.io:183096$$qGLOBAL_SET$$pconf$$pSTI
000183096 917Z8 $$x112915
000183096 917Z8 $$x112915
000183096 937__ $$aEPFL-CONF-183096
000183096 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000183096 980__ $$aCONF