Runtime 3-D Stacked Cache Management for Chip-Multiprocessors

These-dimensional (3-D) memory stacking is one of the most promising solutions to memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which takes advantage of the lower latencies through vertical interconnect as well as the runtime memory demand of applications which varies dynamically with time. Experimental results show that the proposed method offers performance improvement by up to 26.7% and on average 13.1% compared with the private cache organization.


Published in:
Proceedings of the International Symposium on Quality Electronic Design (ISQED 2013)
Presented at:
The International Symposium on Quality Electronic Design (ISQED 2013), Santa Clara, California, March 4-6, 2013
Year:
2013
Laboratories:




 Record created 2012-12-04, last modified 2018-03-17

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