Cutting-edge CMOS neurochips, which consist of a Microelectrode Array (MEA) manufactured on top of CMOS circuitry, allow the recording of the electrical activity of neural networks in-vitro, and their stimulation. As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital Converters (ADCs) to be integrated on-chip. To relax the requirements on the neurochip’s surface temperature control system, a low-power ADC is targeted1. Among various ADC architectures, the Switched-Capacitor (SC) or Charge-Redistribution Successive Approximation Register (SAR) ADC is best suited for low power and 12-bit resolution. To avoid common-mode errors, the SC SAR ADC uses a differential topology. To decrease area, power, and cost while maintaining 12-bit accuracy, the Binary-Weighted (BW) capacitor array is split into three sub-BW capacitor arrays connected through two series capacitors. A comparator with three preamplifier stages and a latch discriminates voltage differences as small as 200μV while concurrently working with rail-to-rail input signals. The SAR control logic uses only four DFFs for the finite state machine, whereas a classical SAR implementation with shift-registers would use 12 DFFs. Furthermore, a shared register bank contains the output codes and memorizes the position of switches. The SAR ADC will be manufactured in UMC 0.18μm CMOS technology.