000181558 001__ 181558
000181558 005__ 20190316235502.0
000181558 0247_ $$2doi$$a10.1109/MDT.2012.2223191
000181558 022__ $$a0740-7475
000181558 02470 $$2ISI$$a000326979000009
000181558 037__ $$aARTICLE
000181558 245__ $$aDesign Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms
000181558 269__ $$a2013
000181558 260__ $$aPiscataway$$bInstitute of Electrical and Electronics Engineers$$c2013
000181558 336__ $$aJournal Articles
000181558 520__ $$aTraditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there is a wide family of iterative multimedia algorithms that cannot be executed with satisfactory performance on Multi-Processor Systems-on-Chip or Graphics Processing Units. For this reason, new methods to design custom hardware circuits that exploit the intrinsic parallelism of multimedia algorithms are needed. As a consequence, in this paper, we propose a novel design method for the definition of hardware systems optimized for a particular class of multimedia iterative algorithms. We have successfully applied the proposed approach to several real-world case studies, such as iterative convolution filters and the Chambolle algorithm, and the proposed design method has been able to automatically implement, for each one of them, a parallel architecture able to meet real-time performance (up to 72 frames per second for the Chambolle algorithm), with on-chip memory requirements from 2 to 3 orders of magnitude smaller than the state-of-the art approaches.
000181558 6531_ $$aFPGA
000181558 6531_ $$aMPSoC
000181558 6531_ $$areconfiguration
000181558 6531_ $$afine-grained parallelization
000181558 6531_ $$aChambole
000181558 6531_ $$aparallel computing
000181558 6531_ $$asystem-level design
000181558 6531_ $$aembedded systems
000181558 6531_ $$amultimedia systems
000181558 6531_ $$aConvolution filters
000181558 700__ $$0242434$$aRana, Vincenzo$$g182298
000181558 700__ $$0(EPFLAUTH)213378$$aNacci, Alessandro Antonio$$g213378
000181558 700__ $$0242432$$aBeretta, Ivan$$g196973
000181558 700__ $$aSantambrogio, Marco
000181558 700__ $$0240268$$aAtienza Alonso, David$$g169199
000181558 700__ $$aSciuto, Donatella
000181558 773__ $$j30$$k4$$q71-50$$tIEEE Design & Test
000181558 8564_ $$s677288$$uhttps://infoscience.epfl.ch/record/181558/files/DT-2012-01-0013.pdf$$yPreprint$$zPreprint
000181558 909C0 $$0252050$$pESL$$xU11977
000181558 909CO $$ooai:infoscience.tind.io:181558$$pSTI$$particle$$qGLOBAL_SET
000181558 917Z8 $$x169199
000181558 917Z8 $$x148230
000181558 937__ $$aEPFL-ARTICLE-181558
000181558 973__ $$aEPFL$$rREVIEWED$$sPUBLISHED
000181558 980__ $$aARTICLE