000181369 001__ 181369
000181369 005__ 20190316235457.0
000181369 0247_ $$2doi$$a10.1016/j.mee.2010.12.117
000181369 022__ $$a0167-9317
000181369 037__ $$aARTICLE
000181369 245__ $$aAmbipolar silicon nanowire FETs with stenciled-deposited metal gate
000181369 269__ $$a2011
000181369 260__ $$bElsevier$$c2011
000181369 336__ $$aJournal Articles
000181369 520__ $$aWe report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si) and SiO2 layers as well as metal gate patterning using stencil lithography, demonstrated for the first time. FinFETs with stenciled Al gates are successfully co-fabricated with polycrystalline silicon Ω-gated devices. Stencil lithography is envisaged as a key enabler for gate patterning on 3D structures, such as vertically stacked nanowire transistors.
000181369 6531_ $$aSchottky barrier
000181369 6531_ $$aambipolarity
000181369 6531_ $$aSi nanowire
000181369 6531_ $$astencil lithography
000181369 6531_ $$aFET
000181369 6531_ $$asilicide
000181369 700__ $$0242417$$g181895$$aSacchetto, Davide
000181369 700__ $$0245968$$g176597$$aSavu, Veronica
000181369 700__ $$0240269$$g167918$$aDe Micheli, Giovanni
000181369 700__ $$aBrugger, Jürgen$$0240120$$g145781
000181369 700__ $$0240162$$g112194$$aLeblebici, Yusuf
000181369 773__ $$j88$$tMicroelectronic Engineering$$k8$$q2732-2735
000181369 8564_ $$uhttps://infoscience.epfl.ch/record/181369/files/1-s2.0-S0167931711000062-main.pdf$$zn/a$$s986306$$yn/a
000181369 909C0 $$xU11140$$0252283$$pLSI1
000181369 909C0 $$0252051$$pLSM$$xU10325
000181369 909C0 $$xU10321$$0252040$$pLMIS1
000181369 909CO $$qGLOBAL_SET$$pSTI$$pIC$$particle$$ooai:infoscience.tind.io:181369
000181369 917Z8 $$x112915
000181369 937__ $$aEPFL-ARTICLE-181369
000181369 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000181369 980__ $$aARTICLE