Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of the devices (n or p-type). Measurement results on silicon show Ion/Ioff > 106 and S≈64mV/dec (70mV/dec) for p-type and n-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we implement for the first time a fully functional 2-transistor XOR gate to demonstrate the potential of this technology for logic circuit design.


Published in:
Proceedings of the International Electron Devices Meeting (IEDM)
Presented at:
International Electron Devices Meeting (IEDM), San Francisco, California, USA, December 10-12, 2012
Year:
2012
Laboratories:




 Record created 2012-09-10, last modified 2018-03-18

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