Numerical and analytical simulations of Suspended Gate - FET for ultra-low power inverters

This paper proposes, for the first time, the investigation of the SG-FET small slope switch based on a hybrid numerical simulation approach combining ANSYS (TM) Multiphysics and ISE-DESSIS (TM) in a self-consistent system. The proposed hybrid numerical simulations uniquely enables the investigation of the physics of complex Micro-Electro-Mechanical/solid-state devices, such as SG-FET. Abrupt switching and effect of gate charges are demonstrated. The numerical data serves to calibrate an analytical EKV-based SG-FET model, which is the used to design and originally simulate a sub-micron (90nm) scaled SG-FET complementary inverter. It is demonstrated that, due to abrupt switch in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter provides significant power saving (1-2 decades reduction of inverter peak current and practically, no leakage power) compared with traditional CMOS inverter.


Published in:
Essderc 2007: Proceedings Of The 37Th European Solid-State Device Research Conference, 167-170
Presented at:
37th European Solid-State Device Research Conference, Munich, GERMANY, Sep 11-13, 2007
Year:
2007
Publisher:
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa
ISBN:
978-1-4244-1123-8
Keywords:
Laboratories:




 Record created 2012-07-04, last modified 2018-09-13


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