A window-based automatic hardware/software partitioning heuristic

System-level design decisions such as HW/SW partitioning, target architecture selection and scheduler selection are some of the main concerns of current complex system-on-chip (SOC) designs. In this paper, a novel window-based heuristic is proposed that addresses the issue of design space exploration in applications that have a data flow characteristic. The objective in this paper is to partition the application into HW and SW components such that the execution time of the application is minimized while simultaneously satisfying the hard area constraints of the HW units. In this algorithm, the search space is divided into smaller intervals, referred to as windows. For each window the full search is performed to find the optimum partitioning and scheduling solution for that specific window. Moreover, in this paper a novel indexing mechanism is presented for identifying the nodes in the task graph. The proposed index specifies not only the relation of each node with respect to the other nodes in the graph, but also its position in the task graph. With the help of the proposed windowing and indexing techniques, the time required for partitioning is reduced significantly. Simulation results indicate that the proposed algorithm improves the search time by 74% compared to conventional optimization heuristics namely Genetic Algorithm (GA), Simulated Annealing (SA) and Tabu Search (TS), while providing comparable results in terms of the overall execution time of the partitioned system.

Published in:
Arabian Journal For Science And Engineering, 32, 27-40
Presented at:
18th International Conference on Microelectronics (ICM 2006), Dhahran, SAUDI ARABIA, Dec 16-18, 2006

 Record created 2012-07-04, last modified 2018-09-13

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