Tunneling Field Effect Transistors (TFET) are promising devices to respond to the demanding requirements of future technology nodes. The benefits of the TFETs are linked to their sub-60mV/decade sub-threshold swing, a prerequisite for scaling the supply voltage well below 1V. Main research efforts are currently dedicated to improving the on current (ION) level in a TFET. However, from the circuit point of view the device capacitances are equally important. It is known that the drain-to-gate capacitance in a TFET is almost equal to the gate capacitance in moderate and strong inversion regimes. Due to enhanced Miller Effect [1], they are known to exhibit large over/undershoot in transient operation as compared to CMOS. Therefore, the effort on improving ION should be simultaneous to an effort of reducing the Miller capacitance (CMILLER). This work proposes a new architecture which addresses both these issues.