Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to align the components. The minimization of the water-air interface is the driving force. Most studies were performed with a completely wetted chip surface with a resulting alignment of die periphery to carrier. This achieves a maximal die-pad to carrier-pad alignment quality equal to the dicing accuracy, which is typically +/- 25 mu m. To further improve the pad-to-pad alignment accuracy, we propose a pad-assisted SA technique. With an initial placement quality of less than half a pad pitch, this technique achieves submicron SA accuracy. Furthermore, we extend the process to dies with Au studs needed in later thermo-compression bonding. Design rules to design a stable process are reported. A meniscus minimization model is built, which explains the experimental results and helps to design new SA patterns.

Published in:
2011 IEEE 61St Electronic Components and Technology Conference (ECTC), 1153-1159
Presented at:
IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, May 31-Jun 03, 2011
IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

 Record created 2012-06-25, last modified 2018-03-17

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