A 10-bit 50-MS/s Redundant SAR ADC with Split Capacitive-Array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 1 mu m CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.


Published in:
Analog Integrated Circuits and Signal Processing, 71, 3, 583-589
Year:
2012
Publisher:
Springer Verlag
ISSN:
0925-1030
Keywords:
Laboratories:




 Record created 2012-06-14, last modified 2018-01-28


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)