Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, which are further aggravated by process parameter variations. A replica bit-line (BL) technique, previously proposed for SRAM, is adapted to speed up the multilevel read operation at a negligible area-increase. Moreover, the same replica column is used to improve the write access time. An 8-kb DRAM macro implemented in 90-nm CMOS technology shows that the replica column is able to successfully track die-to-die process, voltage, and temperature variations to generate control signals with optimum delay. Finally, Monte-Carlo simulations show that a small timing margin of 100 ps is sufficient to also cope with within-die process variations.


Published in:
2012 Ieee 10Th International New Circuits And Systems Conference (Newcas), 77-80
Presented at:
IEEE International NEWCAS Conference, Montréal, Canada, June 17-20, 2012
Year:
2012
Publisher:
New York, Ieee
ISBN:
978-1-4673-0859-5
Laboratories:




 Record created 2012-06-12, last modified 2018-09-13

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