Single-photon Avalanche Diodes in sub-100nm Standard CMOS Technologies

Single-photon avalanche diodes (SPADs) are evaluated in two sub-100nm CMOS technologies. Several geometries are implemented, whereas premature edge breakdown (PEB) prevention is achieved with n-well rings. The octagonal SPADs are implemented in 90nm and 65nm standard CMOS technologies. Full characterization of SPAD performance is carried out as a function of bias and temperature. To the best of our knowledge, this is the first report of SPAD in any 65nm CMOS technology.


Published in:
Proc. Intl. Image Sensor Workshop (IISW)
Presented at:
Intl. Image Sensor Workshop (IISW), June, 2011
Year:
2011
Keywords:
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 Record created 2012-06-12, last modified 2018-03-17

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