000176907 001__ 176907
000176907 005__ 20190316235352.0
000176907 020__ $$a978-1-4673-1036-9
000176907 02470 $$2ISI$$a000309266000045
000176907 037__ $$aCONF
000176907 245__ $$aThe Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter
000176907 269__ $$a2012
000176907 260__ $$bIeee$$c2012$$aNew York
000176907 300__ $$a8
000176907 336__ $$aConference Papers
000176907 490__ $$aInternational Symposium on Quality Electronic Design
000176907 520__ $$aIn modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skew and jitter is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (> 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (<13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.
000176907 6531_ $$aclock distribution network
000176907 6531_ $$aclock jitter
000176907 6531_ $$aclock skew
000176907 6531_ $$askitter
000176907 6531_ $$aprocess variations
000176907 6531_ $$apower supply noise
000176907 700__ $$0242420$$g183772$$aXu, Hu
000176907 700__ $$0241997$$g188258$$aPavlidis, Vasileios
000176907 700__ $$g206853$$aBurleson, Wayne$$0(EPFLAUTH)206853
000176907 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000176907 7112_ $$dMarch 19-21, 2012$$cSanta Clara, California, USA$$aIEEE International Symposium on Quality Electronic Design (ISQED)
000176907 773__ $$tProceedings of IEEE International Symposium on Quality Electronic Design (ISQED)$$q322-329
000176907 8564_ $$uhttps://infoscience.epfl.ch/record/176907/files/ISQED_12.pdf$$zn/a$$s2021950$$yn/a
000176907 909C0 $$xU11140$$0252283$$pLSI1
000176907 909CO $$pIC$$ooai:infoscience.tind.io:176907$$qGLOBAL_SET$$pconf$$pSTI
000176907 917Z8 $$x112915
000176907 937__ $$aEPFL-CONF-176907
000176907 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000176907 980__ $$aCONF