Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

In this paper, we investigate the benefits of instruction set extensions (ISEs) on a 16-bit microcontroller architecture for software implementations of cryptographic hash functions, using the example of the five SHA-3 final round candidates. We identify the general algorithm bottlenecks, taking into account memory footprints and cycle counts of our optimized reference assembly implementations. We show that our target applications benefit from algorithm-specific ISEs based on finite state machines for address generation, lookup table integration, and extension of computational units through microcoded instructions. The gains in throughput, memory consumption, and the area overhead are assessed, by implementing the modified cores and applications utilizing the developed ISEs. Our results show that with less than 10% additional core area, it is possible to increase the execution speed on average by 172% (ranging from 21% to 703%), while reducing memory requirements on average by more than 40%.


Published in:
2012 Ieee 23Rd International Conference On Application-Specific Systems, Architectures And Processors (Asap), 117-124
Presented at:
23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Delft, The Netherlands, July 9-11, 2012
Year:
2012
Publisher:
New York, Ieee
ISSN:
1063-6862
ISBN:
978-0-7695-4768-8
Keywords:
Laboratories:




 Record created 2012-05-06, last modified 2018-03-17

Publisher's version:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)