Reducing OLTP Instruction Misses With Thread Migration

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from high instruction miss rates since the instruction footprint of OLTP transactions does not fit in today’s L1-I caches. However, modern many-core chips have ample aggregate L1 cache capacity across multiple cores. Looking at the code paths concurrently executing transactions follow, we observe a high degree of repetition both within and across transactions. This work presents TMi a technique that uses thread migration to reduce instruction misses by spreading the footprint of a transaction over multiple L1 caches. TMi is a software-transparent, hardware technique; TMi requires no code instrumentation, and efficiently utilizes available cache capacity. This work evaluates TMi’s potential and shows that it may reduce instruction misses by 51% on average. This work discusses the underlying trade-offs and challenges, such as an increase in data misses, and points to potential solutions.

Published in:
Proceedings of the 8th International Workshop on Data Management on New Hardware (DaMoN 2012)
Presented at:
8th International Workshop on Data Management on New Hardware (DaMoN 2012), Scottsdale, Arizona, USA, May 21, 2012

 Record created 2012-05-01, last modified 2019-03-16

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