Fabrication and characterization of wafer-level deep TSV arrays

Three Dimensional (3D) integration, based on through silicon vias (TSV), has the potential to become a key enabling technology for many applications. TSVs are commonly categorized according to their aspect ratio and diameter. An equally important parameter of the TSV, usually omitted, is their depth. This paper discusses the fabrication process, characterization and detailed failure analysis of deep Cu TSVs, with high aspect ratio. For the proposed process, TSVs are etched on a 380 mu m thick wafer using standard deep reactive ion etching (DRIE). The electroplating is performed in two steps, the first step seals off one side of the TSV using super conformal chemistry, Dow chemical Intervia (TM) 8520 bath, and the second step uses the now partially filled via as a seed layer for a bottom up technique, bath Intervia (TM) 8510 or Intervia (TM) 8520 Dow Chemical. After the electroplating, a chemical-mechanical polishing (CMP) step is used to planarize the wafer, and double-sided metal sputtering and photolithography are performed to connect the TSVs in a daisy chain. A conventional bonding technique, like solder bumps, can be used to bond layers with TSVs.

Published in:
Proceedings of the 62nd Electronic Components and Technology Conference (ECTC), 1625-1630
Presented at:
Electronic Components and Technology Conference (ECTC), San Diego, California, USA, May 29 - June 2, 2012
New York, IEEE

 Record created 2012-02-28, last modified 2018-03-17

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