Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies
Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited for medium sampling frequencies (50-300MSPS) and medium resolutions, i.e. 8 to 14 bits. Having the lowest figure-of-merit (FOM) in its bandwidth and resolution category, this architecture is frequently used for high-bandwidth software-defined radio applications. However, due to the continuous down-scaling trends, designing low-power pipelined ADCs becomes extremely difficult as supply voltages diminish and characteristics of CMOS devices deteriorate (e.g., low intrinsic gain). This thesis addresses these issues in three points: Proposes an analogue technique relaxing the constraints on multiplying D/A converter (MDAC) stages due to low supply voltage and low intrinsic gain, Introduces a power-efficient architecture, Presents an optimization method for exploiting the performance fully. A system-level methodology is developed to investigate different architectural possibilities and to find the one with the lowest power consumption. The architecture of pipelined converters is generalized for fractional gains and analyzed systematically; an optimization toolkit which uses the derived system-level models is developed in MATLAB. Using this approach, this work shows that the power dissipation can be decreased more than 20% with slight modification of inter-stage gains by using general integer and fractional MDACs depending on resolution, operation frequency, and analog blocks. For relaxing the constraints on amplifiers, an MDAC stage incorporating a novel technique for compensating the residual error due to finite amplifier gain is proposed. With this technique, it is shown that high speed and high resolution pipelined ADCs can be designed using simple low-gain amplifiers without gain-boosting. Similar techniques in the literature like time-shifted correlated double sampling (TS-CDS) and time-aligned CDS (TA-CDS) are based on a hold capacitor for storing and subtracting the residual error. This work demonstrates that the selection of the hold capacitance in these techniques has a significant impact on the total power, as much as 46% for individual MDACs. A system-level analysis of TS/TA-CDS stages has been presented and optimal scaling of hold capacitors is demonstrated on example pipeline architectures.
Keywords: ADC ; pipelined converter ; technology scaling ; multiplying D/A converter ; MDAC ; non-integer gain ; optimization ; optimal design ; optimal scaling ; optimization methodology ; hold capacitor ; TS-CDS ; TA-CDS ; analog accuracy improvement ; residual error ; gain insensitive MDAC ; CAN ; convertisseur analogique-numérique pipeline ; mise à l'échelle de la technologie ; convertisseur numérique à analogique multiplicateur (MDAC) ; gain fractionnaire ; optimisation ; conception optimale ; dimensionnement optimal ; méthodologie d'optimisation ; condensateur de maintien ; double échantillonnage corrélé et décalé en temps (TS-CDS) ; double échantillonnage corrélé et aligné en temps (TACDS) ; amélioration de la précision analogique ; erreurs résiduelle ; MDAC insensible au niveau de gainThèse École polytechnique fédérale de Lausanne EPFL, n° 5321 (2012)
Programme doctoral Microsystèmes et Microélectronique
Faculté des sciences et techniques de l'ingénieur
Record created on 2012-02-21, modified on 2016-08-09