Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. © 2011 IEEE.


Published in:
69th Device Research Conference, 111-112
Presented at:
2011 69th Annual Device Research Conference (DRC), Santa Barbara, CA, USA, June 20-22, 2011
Year:
2011
Publisher:
IEEE
Keywords:
Laboratories:




 Record created 2012-01-19, last modified 2018-03-17


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