Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18 mu m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.


Published in:
Proceedings of the 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 5349, 21-30
Presented at:
18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, Sep 10-12, 2008
Year:
2009
Publisher:
Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa
Keywords:
Laboratories:




 Record created 2012-01-09, last modified 2018-03-17


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