Test structure and method for the experimental investigation of internal voltage amplification and surface potential of ferroelectric MOSFETs

In this paper we report the fabrication and detailed electrical characterization of a novel test structure based on Metal-Ferroelectric-Metal-Oxide-Semiconductor transistor with internal metal contact, aiming at extracting the surface potential and the investigation of internal voltage. This structure could possibly be used for the investigation of the differential voltage amplification expected due to negative capacitance effect. The proposed test structure is p-Fe-FET with a thin Al contact in-between the PVDF ferroelectric and a pedestal oxide, enabling access to the internal voltage potential in all the regimes of operations, from weak to strong inversion. Moreover, the capacitances of reference MOS transistor and of Fe-FET can be independently probed. The fabricated p-type Fe-FET has an excellent subthreshold slope of 75 mV/decade, I-on/I-off > 10(7) and I-off in the pA range. Based on voltage and capacitive measurements, the Fe-FET surface potential is experimentally extracted as well as the polarization of the ferroelectric layer. We demonstrate that the internal node voltage amplitude can be controlled by the sweeping conditions of the polarization loops. We propose a first order modeling of the polarization and we report simulations of the internal potential. (C) 2011 Elsevier Ltd. All rights reserved.

Published in:
Solid-State Electronics, 65-66, 151-156
Presented at:
40th European Solid-State Device Research Conference (ESSDERC)/36th European Solid-State Circuits Conference (ESSCIRC), Seville, SPAIN, Sep 14-16, 2010

 Record created 2011-12-29, last modified 2018-03-17

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