An experimental investigation of the surface potential in ferroelectric P(VDF-TrFE) FETs

In this paper we report the fabrication and detailed electrical characterization of a ferroelectric transistor (Fe-FET) aiming at the extraction of its physical threshold voltage. The investigated transistors are fabricated on doped bulk silicon with a gate stack including 10 nm silicon dioxide, 40 nm P(VDF-TrFE) and Au. Based on capacitive measurements, a capacitive divider circuit and a long-channel MOSFET model, we subsequently extract the surface potential psi(S) dependence on the gate voltage and the physical threshold voltage. The experimental data suggest a more abrupt d psi(S)/dV(g) slope, compared with a conventional transistor. A hysteretic behavior, due to the polarization of the P(VDF-TrFE), is observed in the psi(S)-V-g characteristics. (C) 2009 Elsevier B.V. All rights reserved.

Publié dans:
Microelectronic Engineering, 87, 1607-1609
Présenté à:
35th International Conference on Micro-and Nano-Engineering, Ghent, BELGIUM, Sep 28-Oct 01, 2009

 Notice créée le 2011-12-16, modifiée le 2018-09-13

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