000172768 001__ 172768
000172768 005__ 20180913061024.0
000172768 0247_ $$2doi$$a10.1016/j.mee.2009.10.047
000172768 02470 $$2ISI$$a000276300700237
000172768 037__ $$aCONF
000172768 245__ $$aAn experimental investigation of the surface potential in ferroelectric P(VDF-TrFE) FETs
000172768 269__ $$a2010
000172768 260__ $$c2010
000172768 336__ $$aConference Papers
000172768 520__ $$aIn this paper we report the fabrication and detailed electrical characterization of a ferroelectric transistor (Fe-FET) aiming at the extraction of its physical threshold voltage. The investigated transistors are fabricated on doped bulk silicon with a gate stack including 10 nm silicon dioxide, 40 nm P(VDF-TrFE) and Au. Based on capacitive measurements, a capacitive divider circuit and a long-channel MOSFET model, we subsequently extract the surface potential psi(S) dependence on the gate voltage and the physical threshold voltage. The experimental data suggest a more abrupt d psi(S)/dV(g) slope, compared with a conventional transistor. A hysteretic behavior, due to the polarization of the P(VDF-TrFE), is observed in the psi(S)-V-g characteristics. (C) 2009 Elsevier B.V. All rights reserved.
000172768 6531_ $$aPvdf
000172768 6531_ $$aFerroelectric
000172768 6531_ $$aFet
000172768 6531_ $$aFerroelectric
000172768 6531_ $$aCapacitance
000172768 6531_ $$aFabrication
000172768 6531_ $$aElectrical characterization
000172768 700__ $$0244763$$g178462$$aRusu, Alexandru
000172768 700__ $$aSalvatore, Giovanni
000172768 700__ $$aIonescu, Adrian$$g122431$$0241430
000172768 7112_ $$dSep 28-Oct 01, 2009$$cGhent, BELGIUM$$a35th International Conference on Micro-and Nano-Engineering
000172768 773__ $$j87$$tMicroelectronic Engineering$$q1607-1609
000172768 909C0 $$xU10328$$0252177$$pNANOLAB
000172768 909CO $$pconf$$pSTI$$ooai:infoscience.tind.io:172768
000172768 917Z8 $$x198278
000172768 937__ $$aEPFL-CONF-172768
000172768 973__ $$rNON-REVIEWED$$sPUBLISHED$$aEPFL
000172768 980__ $$aCONF