We have investigated an inductively coupled plasma etching recipe using SiCl4 and SF6 with a resulting selectivity >10 for GaN in respect to InAlN. The formation of an etch-resistant layer of AlF3 on InAlN required about 1 min and was noticed by a 4-times-higher initial etch rate on bare InAlN barrier high electron mobility transistors (HEMTs). Comparing devices with and without plasma-treatment below the gate showed no degradation in drain current and gate leakage current for plasma exposure durations shorter than 30s, indicating no plasma-induced damage of the InAlN barrier. Devices etched longer than the required time for the formation of the etch-resistant barrier exhibited a slight decrease in drain current and an increase in gate leakage current which saturated for longer etching-time durations. Finally, we could prove the quality of the recipe by recessing the highly doped 6 nm GaN cap layer of a GaN/InAlN/AlN/GaN heterostructure down to the 2 nm thin InAlN/AlN barrier layer. (C) 2010 The Japan Society of Applied Physics