In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy applied only on critical parts of the circuit. The inherent property of the technique is that the improvement in the maximum frequency the circuit can run is higher for the larger variations. The work shows that the technique can be already applied for 65nm CMOS technology process where a beneficial delay vs. area/power tradeoff can be made. However, a significant benefit is expected for future nanoscale CMOS technologies such as 45nm and 32nm nodes and in low-voltage applications.