This work reports the first complete experimental demonstration and investigation of subthreshold swing, SS, smaller than 60 mV/decade, at room temperature, due to internal voltage amplification in FETs with a Metal-Ferroelectric-Metal-Oxide gate stack. The investigated p-type MOS transistor is a dedicated test structure to explore the negative capacitance effect by probing the internal voltage between the P(VDF-TrFE) and SiO2 dielectric layers of the gate stack. We find that the region of internal surface potential amplification, d psi(s)/dV(g)> 1, corresponds to an S-shape of the polarization versus ferroelectric voltage (associated with negative capacitance). In Fe-FETs the internal voltage amplification could significantly lower their SS, even without reaching sub-60mV/dec values. SSmin as low as 46 to 58 mV/decade and average swings, SSavg, as small as 51 to 59 mV/dec are observed for the first time in a aminor loop hysteretic characteristics of Fe-FETs.