The precise evaluation of the reliability of logic circuits has a significant importance in highly-defective and future nanotechnologies. It allows efficient comparison of fault-tolerance techniques, and enables designs improvement with respect to their reliability figure. This paper presents a novel, accurate and scalable method for modeling the output probability density functions (PDFs) of logic circuits. Our method combines probability theory with concepts from logic synthesis and testing. The PDFs are modeled using the acquired circuit output probability of failure and PDFs of gates in the last two layers of the output cone. Unlike the existing output PDF modeling techniques, the proposed method is directly applicable to standard CMOS design. Simulation results of benchmark circuits demonstrate the accuracy of the method. Several potential applications of the proposed technique include the analysis of averaging (analog) fault-tolerant techniques, fine-grained redundancy insertion, and reliability-driven design optimization.