The performance of a standard MOSFET degrades with the increase in temperature, impacting the power consumption of the device. In this paper, we report the opposite trend, which is reflected in an improvement of main performance factors in ferroelectric FETs (Fe-FETs), when the temperature is increased. We explain our results by Landau's theory, which is also used to develop and validate an analytical model of ferroelectric capacitance. In order to validate the model, we fabricate and dc characterize a fully depleted silicon-on-insulator transistor with 10-nm SiO2 and 40 nm of vinylidene fluoride trifluorethylene P(VDF-TrFE) as a gate stack at different temperatures, ranging from 300 to 400 K. The transconductance and the subthreshold swing of a Fe-FET show a maximum and a minimum in correspondence to the Curie temperature of the ferroelectric, respectively. The proposed model and extraction is valid for any type of ferroelectric materials and Fe-FETs. Finally, this paper demonstrates that the performance degradation in a standard MOSFET (e. g., transconductance and subthreshold swing) at a high temperature of operation could be reduced or even suppressed in a Fe-FET if the Curie temperature of the gate stack is appropriately designed.