Ultra Low Power Multi-Operand Adder Architecture for Subthreshold Circuits

Subthreshold logic can dramatically reduce energy consumption, if the increased circuit delay is of secondary importance. To gain widespread adoption of this design technique (where V-dd < V-th), one of the important consideration is to improve the energy efficiency of the digital circuits through lowering the minimum energy point. In this paper, we propose a Ultra Low Power Multi Operand Adder (ULP-MOA) architecture capable of operating at subthreshold voltages. Using SPICE simulation, we have evaluated the energy and delay performance of the proposed ULP-MOA architecture and compared them with various traditional multi operand adder architectures. We show that the proposed adder architecture has lower optimal voltage point and less energy consumption; e. g. 7 operands, 8 bits consume 13.7 f J at 250mV when compared with the same size traditional ripple carry adder based multi operand adder (RC-MOA) that consumes 22.4 f J at 300mV; representing 63% net energy saving per multi operand addition. In addition, the proposed ULP-MOA has lower delay (271ns) than the RC-MOA (292ns) and same area overhead (1728 transistors).

Published in:
2011 Ieee 54Th International Midwest Symposium On Circuits And Systems (Mwscas), -
Presented at:
54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, SOUTH KOREA, Aug 07-10, 2011
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

 Record created 2011-12-16, last modified 2018-03-17

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