Negative Capacitance Transistor
Silicon technology has advanced through the past four decades at exponential rate both in performance and productivity. Along with the miniaturization, the power demand grew also exponentially. New technologies are studied in order to develop switches that commute faster and, in the near future, we might see an increasing number of hybrid approaches to overcome the limitations CMOS performance. The ferroelectric thin layers have been studied for memory applications, one transistor memory cell, and recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in transistors in order to overcome the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Ferroelectric Semiconductor Field Effect Transistors, Fe-FET. The objective of this thesis is to study the negative capacitance effect of the ferroelectrics that are integrated into the gate stack of a MOS transistor. For this purpose different Ferroelectric Field Effect Transistors (Fe-FETs) have been designed, fabricated and characterized. Due to its remarkable characteristics, like low temperature deposition, medium-k and low leakage current, vinylidene fluoride trifluorethylene, P(VDF-TrFE), an organic ferroelectric copolymer, of 100 nm and 160 nm thickness was integrated into several MOS devices. Three devices were fabricated, a metal-ferroelectric-oxide-semiconductor transistor, a metal-ferroelectric-metal-oxide-metal capacitor and a metal-ferroelectric-metal-oxide-semiconductor transistor. The internal metal was introduced in-between the two dielectrics so that the potential at that point could be probed. For the first time, subthreshold slopes as low as 48mV/dec were obtained over more than three decades of drain current. The polarization was accurately extracted and the S-shape polarization and the negative slope could be observed. The polarization presented both hysteresis and negative slope polarization. A first-order model, that can accurately characterize a Fe-FET without the negative capacitance effect, was developed and validated with the measurements. Furthermore, a model for predicting the subthreshold slope improvement in case of the negative capacitance transistor, based on the Landau's ferroelectric parameters, was presented. Among others, two possible applications of the ferroelectric transistor are highlighted, one a temperature sensor using the metal-ferroelectric-metal-oxide-semiconductor device and the other one is a Schmitt trigger based on the metal-ferroelectric-oxide-semiconductor transistor.
Keywords: Ferroelectric ; MOSFETs ; Fe-FET ; Small Slope Switches ; NC-FET ; Landau's Theory ; P(VDF-TrFE) ; negative capacitance ; Ferroélectrique ; MOSFETs ; Fe-FET ; commutateur à petite pente ; NC-FET ; Théorie de Landau ; P(VDF-TrFE) ; capacité négativeThèse École polytechnique fédérale de Lausanne EPFL, n° 5276 (2012)
Programme doctoral Microsystèmes et Microélectronique
Faculté des sciences et techniques de l'ingénieur
Institut de génie électrique et électronique
Laboratoire des dispositifs nanoélectroniques
Record created on 2011-11-21, modified on 2016-08-09