This paper describes a pipeline synthesis and optimization technique that increases data throughput of FPGA-based system using minimum pipeline resources. The technique is applied on \CAL dataflow language, and designed based on relations, matrices and graphs. First, the initial As-Soon-As-Possible (ASAP) and As-Late-As-Possible (ALAP) schedules, and the corresponding mobility of operators are generated. From this, operator coloring technique is used on conflict and nonconflict directed graphs using recursive functions and explicit stack mechanisms. For each feasible number of pipeline stages, a pipeline schedule with minimum total register width is taken as an optimal coloring, which is then automatically transformed to a description in \CAL. The generated pipelined \CAL descriptions are finally synthesized to HDL for FPGA implementation. Experimental results of three video processing applications demonstrate up to 3.9x higher throughput for pipelined compared to non-pipelined implementations, and average total pipeline register width reduction of up to 39.6% and 49.9% between the optimal, and ASAP and ALAP pipeline schedules respectively.