Several Hall sensor configurations have been integrated in CMOS technology and analyzed in terms of offset at room temperature and offset drift. We looked for the best geometry that would minimize the offset and its drift. The targeted specification was 30 T for offset at room temperature and 0.3 T/C for the drift. The measurement setup developed allows a clean, reliable and fast analysis of a high number of the same type of cell, located on different positions on the chip. Geometrical correction factor maximization was also performed for small sensing contacts Hall structures in order to ensure maximum sensitivity. © 2011 IEEE.