An 8-bit low-power ADC array for CMOS image sensors

The paper presents an original analog-to-digital converter (ADC) array meeting the constraining requirements in resolution, speed, size, and low power consumption of high-performance low-cost video cameras. The converter array is based on ADC cells relying on a cyclic redundant signed digit (RSD) algorithm supporting comparators with extended tolerance. A prototype ADC array composed of 32 converters was integrated in a 1 μm CMOS process and tested. It is featuring an 8 bit resolution for an active area of 2.1 mm2, and a power consumption of 4 mW at a sampling rate of 4.2 MS/s, with a voltage supply of 2.6 V. Typical DNL and INL values of -0.5/+0.2 and ±0.4 LSB, respectively, were measured for each ADC cell. Moreover, an overall SNR of 45 dB can be achieved with a digital off-chip offset compensation.


Published in:
Proceedings of the 1998 IEEE International Conference on Electronics, Circuits and Systems, 1, 147-150
Presented at:
1998 IEEE International Conference on Electronics, Circuits and Systems, Lisbon, 07 Sep 1998-10 Sep 1998
Year:
1998
ISBN:
0-7803-5008-1
Keywords:
Laboratories:




 Record created 2011-11-04, last modified 2018-06-20


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