Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model
Rideau, D.; Quenette, V.; Garetto, D.; Dornel, E.; Weybright, M.; Manceau, J. P.; Saxod, O.; Tavernier, C.; Jaouen, H.
2010

Résumé

This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description.

Détails

Titre Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model
Auteur(s) Rideau, D. ; Quenette, V. ; Garetto, D. ; Dornel, E. ; Weybright, M. ; Manceau, J. P. ; Saxod, O. ; Tavernier, C. ; Jaouen, H.
Publié dans Proceedings of the 23rd IEEE International Conference on Microelectronic Test Structures (ICMTS)
Pages 210-213
Présenté à 23rd IEEE International Conference on Microelectronic Test Structures (ICMTS), Hiroshima, Japan, March 22-25, 2010
Date 2010
Editeur Piscataway, NJ, USA, IEEE Service Center
Mots-clés (libres)
DOI https://doi.org/10.1109/ICMTS.2010.5466816
Laboratoires LSM
Le document apparaît dans Production scientifique et compétences > STI - Faculté des sciences et techniques de l'ingénieur > IEM - Institute of Electrical and Micro Engineering > LSM - Laboratoire de systèmes microélectroniques
Papiers de conférence
Travail produit à l'EPFL
Publié
Date de création de la notice 2011-10-31