Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model

This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description.


Published in:
Proceedings of the 23rd IEEE International Conference on Microelectronic Test Structures (ICMTS), 210-213
Presented at:
23rd IEEE International Conference on Microelectronic Test Structures (ICMTS), Hiroshima, Japan, March 22-25, 2010
Year:
2010
Publisher:
Piscataway, NJ, USA, IEEE Service Center
Keywords:
Laboratories:




 Record created 2011-10-31, last modified 2018-03-17


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