Characterization and physical modeling of endurance in embedded non-volatile memory technology

Transient and endurance mechanisms in highperformance embedded non-volatile memory flash devices are investigated in detail. An extraction methodology combining measurements on equivalent transistors and flash cells is proposed to discriminate the effects of defects on program/erase (P/E) efficiencies and on DC characteristics. A semi-analytical multiphonon-assisted charge trapping model is used to investigate the role and the impact of trapped charges on channel hotelectron injection and Fowler-Nordheim efficiencies, threshold voltage variations and endurance characteristics. © 2011 IEEE.


Published in:
Proceedings of the 3rd IEEE International Memory Workshop
Presented at:
3rd IEEE International Memory Workshop, Monterey, California, USA, May 22-25, 2011
Year:
2011
Laboratories:




 Record created 2011-10-31, last modified 2018-03-17

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