Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing
2011
Details
Title
Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing
Author(s)
Kheradmand Boroujeni, Bahman ; Piguet, Christian ; Leblebici, Yusuf
Published in
Journal of Low Power Electronics
Volume
7
Issue
2
Pages
285-293
Date
2011
Keywords
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Peer-reviewed publications
Work produced at EPFL
Journal Articles
Published
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Peer-reviewed publications
Work produced at EPFL
Journal Articles
Published
Record creation date
2011-09-04