Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders


Published in:
Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS), 1772-1775
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011
Year:
2011
Laboratories:




 Record created 2011-08-21, last modified 2018-03-18


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