Area- and throughput-optimized VLSI architecture of sphere decoding


Published in:
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 189-194
Presented at:
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, 27-29 09 2010
Year:
2010
Publisher:
IEEE
Laboratories:




 Record created 2011-08-21, last modified 2018-09-13


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