A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication

this paper describes a phase-locked loop (PLL) designed for clock multiplication in a LVDS transmitter. The PLL consists of a novel low-jitter charge-pump, a fully differential ring-oscillator based VCO, a dynamic-logic PFD, a 2nd order passive loop filter and a digital frequency divider. The PLL exhibits simultaneously low jitter and low power consumption. It has been integrated into a 0.35 um CMOS process, occupying 0.09 mm2 of silicon area. For a 350 MHz output frequency, the circuit features a cycle-to-cycle jitter of 7.1 ps rms and 65 ps peak-to-peak. At that frequency, the PLL consumes 12 mW from a supply voltage of 3.3 V.

Published in:
Proceedings of the European Solid-State Circuits Conference (ESSCIRC 2006), 174-177
Presented at:
European Solid-State Circuits Conference (ESSCIRC 2006), Montreux, Switzerland, September 18-22, 2006

Note: The status of this file is: EPFL only

 Record created 2011-07-29, last modified 2018-03-17

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