Conference paper

Flexible and Low Power Binary-Tree Current Mode Min/Max Nonlinear Filters Realized in CMOS Technology

In this paper we present current mode, programmable, binary tree MIN/MAX filters designed for nonlinear data processing. Proposed circuits can be used in image filtration, to realize operations such as erosion or dilatation that are useful in noise reduction or correction of objects in the images. Two kinds of filters are proposed. The first one has been designed for 1-dimensional (1-D) signal processing. Samples of the input signal are being stored in the circular analog delay line. Each sample remains on its fixed position in the delay line as long as is overwritten by the new sample after number of clock phases that is equal to the filter order N. As a result, only one analog delay element is updated with every new signal sample. This minimizes both the power dissipation and errors that in other types of filter structures are associated with data rewriting. The 2-D filters proposed in this paper are the natural extension of 1-D filters. These filters have been realized as universal 2-D structures, which can be easily reprogrammed to perform various nonlinear operations. The experimental 2-D image processor with 64 inputs (8x8 cluster) has been designed in CMOS 0.18um technology and successfully tested in HSPICE simulations. Designed circuit enables parallel calculation of 64 pixels with the rate that is equal to 500 thousands image frames per second, dissipating power about 20 uW. Resultant data rate is therefore equal to 32 MSamples/s and energy consumed per one calculated pixel is about 1 pJ.


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